Model-Based Fill

ABSTRACT

Various aspects of this disclosure relate to increasing pattern density in a circuit layout design of a circuit layer so as to control the thickness of material in a manufactured integrated circuit. For example, a layer in circuit design may be divided into separate areas, and a target thickness range may be established for all of the tiles in the integrated circuit design. Each area may be analyzed to determine if it has a sufficient pattern density for a thickness estimation model to accurately estimate its expected material thickness upon manufacture. Each tile may be analyzed to determine if the expected thickness for that tile is within the target thickness range.

RELATED APPLICATIONS

This application claims priority under 35 U.S.C. §119 to U.S.Provisional Patent Application No. 61/153,43 entitled “Model-BasedFill,” filed on Feb. 19, 2009, naming Shohdy Abd Elkader and Craig M.Larsen as inventors, which application is incorporated entirely hereinby reference.

FIELD OF THE INVENTION

The present invention relates to various techniques and tools to assistin the design of circuits, such as integrated circuits. Various aspectsof the present invention are particularly applicable to adjusting thepattern density of a material layer of an integrated circuit design, tocontrol a thickness of the material in an integrated circuitmanufactured from the integrated circuit design.

BACKGROUND OF THE INVENTION

Electronic circuits, such as integrated microcircuits, are used in avariety of products, from automobiles to microwaves to personalcomputers. Designing and fabricating microcircuit devices typicallyinvolves many steps, known as a “design flow.” The particular steps of adesign flow are highly dependent upon the type of microcircuit, itscomplexity, the design team, and the microcircuit fabricator or foundrythat will manufacture the microcircuit. Software and hardware “tools”then verify the design at various stages of the design flow by runningsoftware simulators and/or hardware emulators, and errors in the designare corrected.

Several steps are common to all design flows. First, the specificationsfor the new microcircuit are described in terms of logical operations,typically using a hardware design language (HDL), such as VHDL. Afterthe accuracy of the logical design is confirmed, the logical design isconverted into device design data by synthesis software. The devicedesign data, in the form of a schematic, represents the specificelectronic devices, such as transistors, resistors, and capacitors,which will achieve the desired logical result and theirinterconnections. Preliminary timing estimates for portions of thecircuit may also be made at this stage, using an assumed characteristicspeed for each device. This schematic generally corresponds to the levelof representation displayed in conventional circuit diagrams.

Once the relationships between circuit devices have been established,the design is again transformed into physical design data describingspecific geometric elements. These geometric elements, often referred toas a “layout” design, define the shapes that will be created in variousmaterials to form the specified circuit devices. Custom layout editors,such as Mentor Graphics' IC Station or Cadence's Virtuoso are commonlyused for this task. Automated place and route tools also will frequentlybe used to define the physical layouts, especially of wires that will beused to interconnect the circuit devices. Each layer of the microcircuitwill have a corresponding layer representation in the layout design, andthe geometric shapes described in a layer representation will define therelative locations of the circuit elements that will make up the circuitdevice. For example, shapes in the layer representation of a metal layerwill define the locations of the metal wires used to connect the circuitdevices. Thus, the layout design data represents the patterns that willbe written onto masks to fabricate the desired microcircuit using, forexample, photolithographic processes.

Modern integrated circuits typically will be formed of multiple layersof material, such as metal, diffusion material, and polysilicon. Duringthe manufacturing process, layers of material are formed on top of oneanother sequentially. After each layer is created, portions of the layerare removed to form structures. Together, the structures of materialform the functional circuit devices, such as transistors, capacitors andresistors, which will make up the integrated circuit. Before a new layeris formed over the structures in an existing layer, however, theexisting layer must be polished to ensure planarity. Polishing using anyof various types of polishing processes sometimes will generically bereferred to as “planarization.”

One problem with conventional planarization methods is that differentmaterials will have different densities, so softer materials will bepolished more than harder materials. As a result, a layer's surface maybecome uneven, causing the next layer to be more uneven. In somesituations, the uppermost layers of material may have a very irregularsurface topography. Such irregular surface topographies may cause avariety of flaws in the circuit structures, such as holes, loss ofcontact, and other manufacturing defects.

To improve the planarity of a layer of material, the integrated circuitdesigner (or manufacturer) often will analyze a circuit layout designfor empty regions in the layer. That is, the designer or manufacturerwill review the density of the geometric elements representing thestructures that will be formed in the layer (sometimes referred to as“pattern density”), to identify regions that are empty of thesegeometric elements. The designer or manufacturer will then modify thecircuit layout design to fill these empty regions with data representing“dummy” or “fill” geometric elements. That is, the designer ormanufacturer will increase the density of the geometric elements in thecircuit layout design for the layer by adding geometric elements thatwill form non-functional structures. When the circuit is manufactured,these “fill” structures will be formed alongside the “functional”structures (i.e., the structures used to form functional circuitdevices), so that the overall surface of the layer is relatively flat.This type of corrective technique will often be implemented using asoftware application for identifying and manipulating structures definedin a circuit layout design, such as the CALIBRE® verification andmanufacturability software tools available from Mentor Graphics®Corporation of Wilsonville, Oreg.

While this corrective technique usually improves the planarity of layersin an integrated circuit, its implementation is often unpredictable.Many conventional fill addition processes add fill geometric elements tothe integrated circuit design in order to bring the overall geometricelement density up to a target value. While increasing the patterndensity in a layer of the design typically will increase thecorresponding thickness of the material in the manufactured integratedcircuit, the amount of the increase can be very unpredictable. Inaddition to being dependent upon the density of the geometric elementsin the integrated circuit design, the material thickness also isdependent upon the ration of the perimeter length of the geometricelements to the area occupied by the geometric elements. Conventionalfill techniques do not take into account this perimeter-to-area ratiofor the geometric elements, making the selection of the fill densityamount to be added to an integrated circuit design unpredictable.

Adding unnecessary fill structures may increase the capacitance of thematerial layer. If the designer or manufacturer inadvertently fills toomuch of the empty regions with fill geometric elements, or places fillgeometric elements too close to functional geometric elements, theincreased capacitance in the manufactured material layer may cause thesurrounding circuit devices to exceed their minimum timing requirements.Still further, each additional fill geometric element in a design mayincrease the time and complexity of optical proximity correctionprocessing or resolution enhancement technology processing of thecircuit layout design prior to manufacture.

BRIEF SUMMARY OF THE INVENTION

Advantageously, various examples of the invention provide techniques forincreasing the pattern density in a circuit layout design of a circuitlayer so as to control the thickness of the corresponding material inthe manufactured integrated circuit. According to variousimplementations of the invention, a layer in circuit design is dividedinto separate areas, sometimes referred to as “windows” or “tiles.” Eachof the windows is analyzed to identify the tile with the highestfunctional density, which inherently determines the largest minimum tilethickness. The estimated thickness of this tile is then selected as abase thickness, and, based upon an allowable thickness variation (whichmay be determined by a designer or manufacturer), a target thicknessrange is established for all of the tiles in the integrated circuitdesign.

Initially, each tile may be analyzed to determine if it has a sufficientpattern density for a thickness estimation model to accurately estimateits expected material thickness upon manufacture. With someimplementations of the invention, if a tile's pattern density is toosmall for its expected thickness to be accurately estimated, then thattile is ignored. With still other implementations of the invention,however, fill geometric elements may be added to the tile, in order toincrease its pattern density up to a level that the thickness estimationmodel can use to accurately estimate the corresponding materialthickness for that tile upon manufacture.

Next, each tile is analyzed to determine of the expected thickness forthat tile is within the target thickness range. With someimplementations of the invention, this analysis may be performed byemploying the thickness estimation model directly. With still otherimplementations of the invention, however, the expected thickness ofeach tile can be estimated using a look up table generated using thethickness estimation model. More particularly, various embodiments ofthe invention may employ the thickness estimation model to generate atable of expected thickness values corresponding to combinations ofgeometric element density values and geometric element perimeter-to-arearatio values (or other values correlating to geometric element densityvalues and/or geometric element perimeter-to-area ratio values). If theestimated thickness of a tile is outside of the target thickness range,then the tile is slated for further processing.

If a tile must be processed further, then the thickness estimation modelis used to identify a geometric element density value (or correlatingvalue) and a geometric element perimeter-to-area ratio value (orcorrelating value) combination for the tile that will provide anexpected thickness within the target thickness range. With someimplementations of the invention, these values can be calculateddirectly using the thickness estimation model. As previously noted,however, some implementations of the invention may employ a lookup tableof expected thickness values corresponding to combinations of geometricelement density values and geometric element perimeter-to-area ratiovalues (or other values correlating to geometric element density valuesand/or geometric element perimeter-to-area ratio values). By using thislookup table, the entries of the table can be scanned until an entry isidentified reflecting a geometric element density value greater than thecurrent geometric element density value of the tile, a geometric elementperimeter-to-area ratio value greater than the current geometric elementperimeter-to-area ratio value of the tile, and an expected thicknesswithin the target thickness range.

Once a satisfactory combination of a geometric element density value (orcorrelating value), a geometric element perimeter-to-area ratio value(or correlating value) and a thickness value has been selected, then ashape for fill geometric elements is chosen from a plurality of fillshape options. Next, the amount of geometric elements with the chosenfill shape required to increase the geometric element density value (orcorrelating value) of the tile to the selected geometric element densityvalue (or correlating value) is determined. Also, the geometric elementperimeter-to-area ratio value (or correlating value) that would resultfrom adding this amount of geometric elements with the chosen fill shapeto the tile is determined. These two values can then be employed, eitherby using the lookup table or the thickness estimation model directly, toestimate an expected thickness of the tile upon addition of the amountof geometric elements with the chosen fill shape.

If the estimated expected thickness of the tile is within the targetthickness range, then that amount of fill geometric elements with thechosen fill shape is added to the tile. The fill geometric elements canbe added to the integrated circuit design using any conventional filladdition tool, such as the SmartFill tool included in the CALIBRE®family of integrated circuit design verification tools available fromMentor Graphics Corporation of Wilsonville, Oreg. If the estimatedexpected thickness of the tile is not within the target thickness range,however, then a new fill shape is selected, a new amount of fillgeometric elements with the new shape to be added to the tile isdetermined, and the new geometric element perimeter-to-area ratio value(or correlating value) for this amount of fill geometric elements isdetermined. This process is repeated until a fill shape is chosen thatprovides an expected thickness for the tile within the target thicknessrange. If the choice of fill shapes is exhausted before a satisfactoryexpected thickness is obtained, then a new geometric element densityvalue (or correlating value) and geometric element perimeter-to-arearatio value (or correlating value) for the tile is selected. Again, thenew combination of values can be determined using the thicknessestimation model, or by using a lookup table generated from thethickness estimation model.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 and 2 illustrate an example of a computing device that may beemployed to implement various examples of the invention.

FIG. 3 illustrates an example of a fill addition tool that may beemployed according to various embodiments of the invention.

FIG. 4 illustrates a flowchart describing a method of selecting fillgeometric elements to be added to an integrated circuit design accordingto various embodiments of the invention.

DETAILED DESCRIPTION OF THE INVENTION Illustrative Operating Environment

Various examples of fill geometric element addition methods and toolsaccording to embodiments of the invention may be implemented by one ormore programmable computing devices executing computer-executablesoftware instructions. Alternately or additionally, various examples offill geometric element addition methods and tools according toembodiments of the invention may be implemented by computer-executablesoftware instructions stored in a computer-readable medium, such as amagnetic or optical storage device, or a solid state memory device.Because these examples of the invention may be implemented usingsoftware instructions, the components and operation of a genericprogrammable computer system on which various embodiments of theinvention may be employed will first be described. Further, because ofthe complexity of some electronic design automation processes and thelarge size of many circuit designs, various electronic design automationtools are configured to operate on a computing system capable ofsimultaneously running multiple processing threads. The components andoperation of a computer network having a host or master computer and oneor more remote or slave computers therefore will be described withreference to FIG. 1. This operating environment is only one example of asuitable operating environment, however, and is not intended to suggestany limitation as to the scope of use or functionality of the invention.

In FIG. 1, the computer network 101 includes a master computer 103. Inthe illustrated example, the master computer 103 is a multi-processorcomputer that includes a plurality of input and output devices 105 and amemory 107. The input and output devices 105 may include any device forreceiving input data from or providing output data to a user. The inputdevices may include, for example, a keyboard, microphone, scanner orpointing device for receiving input from a user. The output devices maythen include a display monitor, speaker, printer or tactile feedbackdevice. These devices and their connections are well known in the art,and thus will not be discussed at length here.

The memory 107 may similarly be implemented using any combination ofcomputer readable media that can be accessed by the master computer 103.The computer readable media may include, for example, microcircuitmemory devices such as read-write memory (RAM), read-only memory (ROM),electronically erasable and programmable read-only memory (EEPROM) orflash memory microcircuit devices, CD-ROM disks, digital video disks(DVD), or other optical storage devices. The computer readable media mayalso include magnetic cassettes, magnetic tapes, magnetic disks or othermagnetic storage devices, punched media, holographic storage devices, orany other medium that can be used to store desired information.

As will be discussed in detail below, the master computer 103 runs asoftware application for performing one or more operations according tovarious examples of the invention. Accordingly, the memory 107 storessoftware instructions 109A that, when executed, will implement asoftware application for performing one or more operations. The memory107 also stores data 109B to be used with the software application. Inthe illustrated embodiment, the data 109B contains process data that thesoftware application uses to perform the operations, at least some ofwhich may be parallel.

The master computer 103 also includes a plurality of processor units 111and an interface device 113. The processor units 111 may be any type ofprocessor device that can be programmed to execute the softwareinstructions 109A, but will conventionally be a microprocessor device.For example, one or more of the processor units 111 may be acommercially generic programmable microprocessor, such as Intel®Pentium® or Xeon™ microprocessors, Advanced Micro Devices Athlon™microprocessors or Motorola 68K/Coldfire® microprocessors. Alternatelyor additionally, one or more of the processor units 111 may be acustom-manufactured processor, such as a microprocessor designed tooptimally perform specific types of mathematical operations. Theinterface device 113, the processor units 111, the memory 107 and theinput/output devices 105 are connected together by a bus 115.

With some implementations of the invention, the master computing device103 may employ one or more processing units 111 having more than oneprocessor core. Accordingly, FIG. 2 illustrates an example of amulti-core processor unit 111 that may be employed with variousembodiments of the invention. As seen in this figure, the processor unit111 includes a plurality of processor cores 201. Each processor core 201includes a computing engine 203 and a memory cache 205. As known tothose of ordinary skill in the art, a computing engine contains logicdevices for performing various computing functions, such as fetchingsoftware instructions and then performing the actions specified in thefetched instructions. These actions may include, for example, adding,subtracting, multiplying, and comparing numbers, performing logicaloperations such as AND, OR, NOR and XOR, and retrieving data. Eachcomputing engine 203 may then use its corresponding memory cache 205 toquickly store and retrieve data and/or instructions for execution.

Each processor core 201 is connected to an interconnect 207. Theparticular construction of the interconnect 207 may vary depending uponthe architecture of the processor unit 201. With some processor cores201, such as the Cell microprocessor created by Sony Corporation,Toshiba Corporation and IBM Corporation, the interconnect 207 may beimplemented as an interconnect bus. With other processor units 201,however, such as the Opteron™ and Athlon™ dual-core processors availablefrom Advanced Micro Devices of Sunnyvale, Calif., the interconnect 207may be implemented as a system request interface device. In any case,the processor cores 201 communicate through the interconnect 207 with aninput/output interfaces 209 and a memory controller 211. Theinput/output interface 209 provides a communication interface betweenthe processor unit 201 and the bus 115. Similarly, the memory controller211 controls the exchange of information between the processor unit 201and the system memory 107. With some implementations of the invention,the processor units 201 may include additional components, such as ahigh-level cache memory accessible shared by the processor cores 201.

While FIG. 2 shows one illustration of a processor unit 201 that may beemployed by some embodiments of the invention, it should be appreciatedthat this illustration is representative only, and is not intended to belimiting. For example, some embodiments of the invention may employ amaster computer 103 with one or more Cell processors. The Cell processoremploys multiple input/output interfaces 209 and multiple memorycontrollers 211. Also, the Cell processor has nine different processorcores 201 of different types. More particularly, it has six or moresynergistic processor elements (SPEs) and a power processor element(PPE). Each synergistic processor element has a vector-type computingengine 203 with 128×128 bit registers, four single-precision floatingpoint computational units, four integer computational units, and a 256KB local store memory that stores both instructions and data. The powerprocessor element then controls that tasks performed by the synergisticprocessor elements. Because of its configuration, the Cell processor canperform some mathematical operations, such as the calculation of fastFourier transforms (FFTs), at substantially higher speeds than manyconventional processors.

It also should be appreciated that, with some implementations, amulti-core processor unit 111 can be used in lieu of multiple, separateprocessor units 111. For example, rather than employing six separateprocessor units 111, an alternate implementation of the invention mayemploy a single processor unit 111 having six cores, two multi-coreprocessor units each having three cores, a multi-core processor unit 111with four cores together with two separate single-core processor units111, etc.

Returning now to FIG. 1, the interface device 113 allows the mastercomputer 103 to communicate with the slave computers 117A, 1157, 117C .. . 117 x through a communication interface. The communication interfacemay be any suitable type of interface including, for example, aconventional wired network connection or an optically transmissive wirednetwork connection. The communication interface may also be a wirelessconnection, such as a wireless optical connection, a radio frequencyconnection, an infrared connection, or even an acoustic connection. Theinterface device 113 translates data and control signals from the mastercomputer 103 and each of the slave computers 117 into network messagesaccording to one or more communication protocols, such as thetransmission control protocol (TCP), the user datagram protocol (UDP),and the Internet protocol (IP). These and other conventionalcommunication protocols are well known in the art, and thus will not bediscussed here in more detail.

Each slave computer 117 may include a memory 119, a processor unit 121,an interface device 122, and, optionally, one more input/output devices125 connected together by a system bus 127. As with the master computer103, the optional input/output devices 125 for the slave computers 117may include any conventional input or output devices, such as keyboards,pointing devices, microphones, display monitors, speakers, and printers.Similarly, the processor units 121 may be any type of conventional orcustom-manufactured programmable processor device. For example, one ormore of the processor units 121 may be commercially generic programmablemicroprocessors, such as Intel® Pentium® or Xeon™ microprocessors,Advanced Micro Devices Athlon™ microprocessors or Motorola 68K/Coldfire®microprocessors. Alternately, one or more of the processor units 121 maybe custom-manufactured processors, such as microprocessors designed tooptimally perform specific types of mathematical operations. Stillfurther, one or more of the processor units 121 may have more than onecore, as described with reference to FIG. 2 above. For example, withsome implementations of the invention, one or more of the processorunits 121 may be a Cell processor. The memory 119 then may beimplemented using any combination of the computer readable mediadiscussed above. Like the interface device 113, the interface devices123 allow the slave computers 117 to communicate with the mastercomputer 103 over the communication interface.

In the illustrated example, the master computer 103 is a multi-processorunit computer with multiple processor units 111, while each slavecomputer 117 has a single processor unit 121. It should be noted,however, that alternate implementations of the invention may employ amaster computer having single processor unit 111. Further, one or moreof the slave computers 117 may have multiple processor units 121,depending upon their intended use, as previously discussed. Also, whileonly a single interface device 113 or 123 is illustrated for both themaster computer 103 and the slave computers, it should be noted that,with alternate embodiments of the invention, either the computer 103,one or more of the slave computers 117, or some combination of both mayuse two or more different interface devices 113 or 123 for communicatingover multiple communication interfaces.

With various examples of the invention, the master computer 103 may beconnected to one or more external data storage devices. These externaldata storage devices may be implemented using any combination ofcomputer readable media that can be accessed by the master computer 103.The computer readable media may include, for example, microcircuitmemory devices such as read-write memory (RAM), read-only memory (ROM),electronically erasable and programmable read-only memory (EEPROM) orflash memory microcircuit devices, CD-ROM disks, digital video disks(DVD), or other optical storage devices. The computer readable media mayalso include magnetic cassettes, magnetic tapes, magnetic disks or othermagnetic storage devices, punched media, holographic storage devices, orany other medium that can be used to store desired information.According to some implementations of the invention, one or more of theslave computers 117 may alternately or additions be connected to one ormore external data storage devices. Typically, these external datastorage devices will include data storage devices that also areconnected to the master computer 103, but they also may be differentfrom any data storage devices accessible by the master computer 103.

It also should be appreciated that the description of the computernetwork illustrated in FIG. 1 and FIG. 2 is provided as an example only,and it not intended to suggest any limitation as to the scope of use orfunctionality of alternate embodiments of the invention.

Fill Addition Tool

As noted above, various embodiments of the invention may be implementedby the execution of software instructions with a programmable computer.For example, some embodiments of the invention may be implemented usingthe CALIBRE® verification and manufacturability software tools availablefrom Mentor Graphics® Corporation of Wilsonville, Oreg. It should beappreciated, however, that other software tools for identifying andmanipulating structures defined in a circuit layout design are known inthe art, and thus may be used to implement various examples of theinvention. Further, a user may employ separate software tools incombination to implement various examples of the invention. For example,a user may employ one or more software tools, such as the CALIBRE®verification and manufacturability software tools, to adjust a densityof each window in a circuit layout design, and use one or more othersoftware tools, such as proprietary software tools, to calculate thedensity of each window.

FIG. 3 illustrates an example of a fill addition tool 301 that may beemployed according to various examples of the invention to increase thepattern density of material layers described in a circuit design layout.As seen in this figure, the fill addition tool 301 includes a filladdition module 303, a tile selection module 305, a design database 307,a thickness estimation lookup table 309, and a fill shape database 311.The fill addition module 303 includes a table entry selection module313, a fill analysis module 315, and a fill selection module 317. Theoperation of each of these components will be discussed in more detailbelow with regard to the flowchart illustrated in FIG. 4.

Initially, an integrated circuit design is provided to the fill additionmodule 303 and the tile selection module 305. With some examples of theinvention, circuit design layout data may be provided directly to thesemodules. Alternately, one or both of these modules may retrieve thecircuit design layout data from the design database 307. With variousexamples of the invention, the circuit design data may be in any desiredtype of data format, such as GDS-II, Oasis, Open Access, Milkyway,LEF/DEF, or Volcano. The circuit design layout data may describe anentire circuit, or it may describe only a portion of a circuit.

Next, the tile selection module 305 divides a material layer in thecircuit design into separate areas, sometimes referred to as “windows”or “tiles.” The tile selection module 305 then analyzes each of thewindows to identify the tile with the highest functional density. Aswill be appreciated by those of ordinary skill in the art, this tileinherently determines the largest minimum tile thickness. The tileselection module 305 then selects the estimated thickness of this tileas a base thickness. The tile selection module 305 also determines atarget material layer thickness range for the integrated circuitmanufactured from the design, by applying an allowable thicknessvariation to the estimated thickness of the selected tile. The allowablethickness variation may be determined by a designer or manufacturer, orestablished automatically by a related electronic design automationprocess (e.g., a design rule check process). This target thickness rangethus is established for all of the tiles in the integrated circuitdesign.

The tile selection module 305 will also analyze each tile, to determineif it has a sufficient pattern density for a thickness estimation modelto accurately estimate its expected material thickness upon manufacture.Most conventional thickness estimation models are accurate for only aspecific range of pattern densities (e.g., 20%-80%), With someimplementations of the invention, if a tile's pattern density is toosmall for its expected thickness to be accurately estimated, then thetile selection module 305 will simply disqualify that tile from furtherprocessing. With still other implementations of the invention, however,the tile selection module 305 may add fill geometric elements to thetile, in order to increase its pattern density up to a level that thethickness estimation model can use to accurately estimate thecorresponding material thickness for that tile upon manufacture.

After the tile selection module 305 has determined the target thicknessrange for the integrated circuit design layer and selected the varioustiles to be processed, it analyzes each selected tile to determine ifthe expected thickness for that tile is within the target thicknessrange. With some implementations of the invention, this analysis may beperformed by employing the thickness estimation model directly (i.e., byplugging the related characteristics of the tile into the model). Withstill other implementations of the invention, however, the tileselection module 305 can estimate the expected thickness of each tilefrom a look up table generated using the thickness estimation model.More particularly, various embodiments of the invention may employ thethickness estimation model to generate the thickness estimation lookuptable 309, a table of expected thickness values corresponding tocombinations of geometric element density values and geometric elementperimeter-to-area ratio values (or other values correlating to geometricelement density values and/or geometric element perimeter-to-area ratiovalues) for all possible fill geometric element combinations. If theestimated thickness of a tile is outside of the target thickness range,then the tile selection module 305 selects that tile for furtherprocessing, and the tile is provided to the fill addition module 303.

Next, the table entry selection module 313 uses the thickness estimationlookup table 309 to identify a target geometric element density value(or correlating value) and a target geometric element perimeter-to-arearatio value (or correlating value) for the tile that will provide anexpected thickness within the target thickness range. More particularly,the table entry selection module 313 will scan the entries of thethickness estimation lookup table 309 until an entry is identifiedreflecting a geometric element density value greater than the currentgeometric element density value of the tile, a geometric elementperimeter-to-area ratio value greater than the current geometric elementperimeter-to-area ratio value of the tile, and an expected thicknesswithin the target thickness range. Of course, alternate implementationsof the invention may use the thickness estimation model itself toidentify a geometric element density value (or correlating value) and ageometric element perimeter-to-area ratio value (or correlating value)combination for the tile that will provide an expected thickness withinthe target thickness range.

Once a satisfactory combination of a geometric element density value (orcorrelating value), a geometric element perimeter-to-area ratio value(or correlating value) and a thickness value has been selected, then thefill analysis module 315 chooses a shape for fill geometric elementsfrom a plurality of fill shape options. Next, fill analysis module 315determines the amount of geometric elements with the chosen fill shaperequired to increase the geometric element density value (or correlatingvalue) of the tile to the selected geometric element density value (orcorrelating value). The fill analysis module 315 also will determine thegeometric element perimeter-to-area ratio value (or correlating value)that would result from adding this amount of geometric elements with thechosen fill shape to the tile.

Next, the fill selection module 317 will use these two values with thethickness estimation lookup table 309 to estimate an expected thicknessof the tile upon addition of the amount of geometric elements with thechosen fill shape. If the estimated expected thickness of the tile iswithin the target thickness range, then the fill selection module 317will add that amount of fill geometric elements with the chosen fillshape to the tile. The fill geometric elements can be added to theintegrated circuit design using any conventional fill addition tool,such as the SmartFill tool included in the CALIBRE® family of integratedcircuit design verification tools available from Mentor GraphicsCorporation of Wilsonville, Oreg.

If, however, the fill selection module 317 determines that the estimatedexpected thickness of the tile is not within the target thickness range,it will provide the tile back to the fill analysis module 315 for a newfill shape to be selected. The fill analysis module 315 will then selecta new fill shape, and determine a new amount of fill geometric elementswith the new shape that must be added to the tile in order to providethe tile with the target geometric element density value from theselected thickness estimation lookup table 309 entry. The fill analysismodule 315 will then also determine the new geometric elementperimeter-to-area ratio value (or correlating value) for this amount offill geometric elements with the new shape, and these values areprovided to the fill selection module 317. This process is repeateduntil a fill shape is chosen that provides an expected thickness for thetile within the target thickness range.

If the choice of fill shapes is exhausted before a satisfactory expectedthickness is obtained, then the fill selection module 317 will providethe tile to the table entry selection module 313 for selection of a newgeometric element density value (or correlating value) and geometricelement perimeter-to-area ratio value (or correlating value) combinationfor the tile. These steps are repeated until satisfactory fill geometricelements have been added to the tile, or until all of the appropriateentries in the thickness estimation lookup table 309 have beenexhausted. In either case, the fill addition module 303 will move on toprocess the next tile provided by the tile selection module 305.

CONCLUSION

While the invention has been described with respect to specific examplesincluding presently preferred modes of carrying out the invention, thoseskilled in the art will appreciate that there are numerous variationsand permutations of the above described systems and techniques that fallwithin the spirit and scope of the invention as set forth in theappended claims. For example, while a specific order of steps has beendescribed above with regard to various examples of the invention, itshould be appreciated that alternate embodiments of the invention mayperform one or more of these steps in an alternate order, perform one ormore of these steps in parallel, or omit one or more of these stepsaltogether.

1. A method of adding fill pattern density to an integrated circuitdesign for controlling a variation in a thickness of material over asurface of an integrated circuit manufactured from the integratedcircuit design, comprising: determining if a window of an integratedcircuit design complies with one or more specified thickness-relatedcriteria, and if the window does not comply with the specified patterndensity criteria, then (a) selecting a fill pattern shape from aplurality of fill pattern shapes, (b) determining an amount of theselected fill pattern shapes to be added to the window for the window tohave a potential pattern density greater than a target pattern density,(c) determining a potential pattern perimeter-to-area ratio for thewindow if the amount of the selected fill pattern shapes is added to thewindow, and (d) determining an expected material thickness for theportion of the integrated circuit design based upon the potentialpattern density and the potential pattern perimeter-to-area ratio;repeating steps (a) through (d) until a successful fill shape isselected that provides an expected material thickness for the windowthat is above a target material thickness; and adding the amount of thesuccessful selected fill shape that provides an expected materialthickness above the specified material thickness to the window.
 2. Themethod recited in claim 1, wherein determining the expected materialthickness for the portion of the integrated circuit design based uponthe determined window pattern perimeter-to-area ratio includes employinga look up table.
 3. The method recited in claim 1, wherein the one ormore specified pattern density criteria includes at least one of: awindow pattern density above a specified pattern density, and a windowpattern perimeter-to-area ratio above a specified patternperimeter-to-area.
 4. The method recited in claim 1, further comprising:if, in step (b), an amount of the selected fill pattern shapes to beadded to the window for the window to have a potential pattern densitygreater than a target pattern density cannot be determined, thenrepeating steps (a) through (d) with a different selected fill shape.